M41T00
Device operation
Figure 4.
Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 5.
Acknowledge sequences
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCLK FROM
MASTER
1
2
8
9
DATA OUTPUT
BY TRANSMITTER
MSB
LSB
DATA OUTPUT
BY RECEIVER
AI00601
Figure 6. Bus timing requirements sequence
SDA
tBUF
tHD:STA
tR
tHD:STA
tF
SCL
tHIGH
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
P
S
tLOW
SR
P
AI00589
1. P = STOP and S = START
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