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M41T00M6F 参数 Datasheet PDF下载

M41T00M6F图片预览
型号: M41T00M6F
PDF下载: 下载PDF文件 查看货源
内容描述: 串行实时时钟 [Serial real-time clock]
分类和应用: 计时器或实时时钟微控制器和处理器外围集成电路光电二极管PC
文件页数/大小: 25 页 / 206 K
品牌: STMICROELECTRONICS [ ST ]
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M41T00 clock operation  
M41T00  
3
M41T00 clock operation  
The eight byte clock register (see Table 5) is used to both set the clock and to read the date  
and time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are  
contained within the first three registers. Bits D6 and D7 of clock register 2 (century/hours  
register) contain the century enable bit (CEB) and the century bit (CB). Setting CEB to a '1'  
will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century  
(depending upon its initial state). If CEB is set to a '0', CB will not toggle. Bits D0 through D2  
of register 3 contain the day (day of week). Registers 4, 5 and 6 contain the date (day of  
month), month and years. The final register is the control register (this is described in the  
clock calibration section). Bit D7 of register 0 contains the STOP bit (ST). Setting this bit to a  
'1' will cause the oscillator to stop. If the device is expected to spend a significant amount of  
time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0'  
the oscillator restarts within one second.  
Note:  
In order to guarantee oscillator start-up after the initial power-up, set the ST bit to a '1,' then  
reset this bit to a '0.' This sequence enables a “kick start” circuit which aids the oscillator  
start-up during worst case conditions of voltage and temperature.  
The seven clock registers may be read one byte at a time, or in a sequential block. The  
control register (address location 7) may be accessed independently. Provision has been  
made to ensure that a clock update does not occur while any of the seven clock addresses  
are being read. If a clock address is being read, an update of the clock registers will be  
delayed by 250 ms to allow the read to be completed before the update occurs. This will  
prevent a transition of data during the read.  
Note:  
Note: This 250 ms delay affects only the clock register update and does not alter the actual  
clock time.  
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