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M25PE10-VMN6TG 参数 Datasheet PDF下载

M25PE10-VMN6TG图片预览
型号: M25PE10-VMN6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 1和2兆位,低电压,页面可擦除串行闪存产品与字节变性, 33兆赫的SPI总线,标准引脚输出 [1 and 2 Mbit, Low Voltage, Page-Erasable Serial Flash Memories with Byte-Alterability, 33 MHz SPI Bus, Standard Pin-out]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 37 页 / 483 K
品牌: STMICROELECTRONICS [ ST ]
 浏览型号M25PE10-VMN6TG的Datasheet PDF文件第9页浏览型号M25PE10-VMN6TG的Datasheet PDF文件第10页浏览型号M25PE10-VMN6TG的Datasheet PDF文件第11页浏览型号M25PE10-VMN6TG的Datasheet PDF文件第12页浏览型号M25PE10-VMN6TG的Datasheet PDF文件第14页浏览型号M25PE10-VMN6TG的Datasheet PDF文件第15页浏览型号M25PE10-VMN6TG的Datasheet PDF文件第16页浏览型号M25PE10-VMN6TG的Datasheet PDF文件第17页  
M25PE10, M25PE20  
Write Enable (WREN)  
The Write Enable (WREN) instruction (Figure 8.)  
sets the Write Enable Latch (WEL) bit.  
The Write Enable Latch (WEL) bit must be set pri-  
or to every Page Write (PW), Page Program (PP),  
Page Erase (PE), and Sector Erase (SE) instruc-  
tion.  
The Write Enable (WREN) instruction is entered  
by driving Chip Select (S) Low, sending the in-  
struction code, and then driving Chip Select (S)  
High.  
Figure 8. Write Enable (WREN) Instruction Sequence  
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction  
High Impedance  
AI02281E  
Write Disable (WRDI)  
The Write Disable (WRDI) instruction (Figure 9.)  
resets the Write Enable Latch (WEL) bit.  
The Write Disable (WRDI) instruction is entered by  
driving Chip Select (S) Low, sending the instruc-  
tion code, and then driving Chip Select (S) High.  
The Write Enable Latch (WEL) bit is reset under  
the following conditions:  
Power-up  
Write Disable (WRDI) instruction completion  
Page Write (PW) instruction completion  
Page Program (PP) instruction completion  
Page Erase (PE) instruction completion  
Sector Erase (SE) instruction completion  
Figure 9. Write Disable (WRDI) Instruction Sequence  
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction  
High Impedance  
AI03750D  
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