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M25PE10-VMN6TG 参数 Datasheet PDF下载

M25PE10-VMN6TG图片预览
型号: M25PE10-VMN6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 1和2兆位,低电压,页面可擦除串行闪存产品与字节变性, 33兆赫的SPI总线,标准引脚输出 [1 and 2 Mbit, Low Voltage, Page-Erasable Serial Flash Memories with Byte-Alterability, 33 MHz SPI Bus, Standard Pin-out]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 37 页 / 483 K
品牌: STMICROELECTRONICS [ ST ]
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M25PE10, M25PE20  
INSTRUCTIONS  
All instructions, addresses and data are shifted in  
and out of the device, most significant bit first.  
Serial Data Input (D) is sampled on the first rising  
edge of Serial Clock (C) after Chip Select (S) is  
driven Low. Then, the one-Byte instruction code  
must be shifted in to the device, most significant bit  
first, on Serial Data Input (D), each bit being  
latched on the rising edges of Serial Clock (C).  
quence. Chip Select (S) can be driven High after  
any bit of the data-out sequence is being shifted  
out.  
In the case of a Page Write (PW), Page Program  
(PP), Page Erase (PE), Sector Erase (SE), Write  
Enable (WREN), Write Disable (WRDI), Deep  
Power-down (DP) or Release from Deep Power-  
down (RDP) instruction, Chip Select (S) must be  
driven High exactly at a Byte boundary, otherwise  
the instruction is rejected, and is not executed.  
That is, Chip Select (S) must driven High when the  
number of clock pulses after Chip Select (S) being  
driven Low is an exact multiple of eight.  
All attempts to access the memory array during a  
Write cycle, Program cycle or Erase cycle are ig-  
nored, and the internal Write cycle, Program cycle  
or Erase cycle continues unaffected.  
The instruction set is listed in Table 5.  
Every instruction sequence starts with a one-Byte  
instruction code. Depending on the instruction,  
this might be followed by address Bytes, or by data  
Bytes, or by both or none.  
In the case of a Read Data Bytes (READ), Read  
Data Bytes at Higher Speed (Fast_Read) or Read  
Status Register (RDSR) instruction, the shifted-in  
instruction sequence is followed by a data-out se-  
Table 5. Instruction Set  
Address Dummy  
Data  
Bytes  
Instruction  
Description  
Write Enable  
One-Byte Instruction Code  
Bytes  
Bytes  
WREN  
WRDI  
RDID  
0000 0110  
0000 0100  
1001 1111  
0000 0101  
0000 0011  
0000 1011  
0000 1010  
0000 0010  
1101 1011  
1101 1000  
1011 1001  
1010 1011  
06h  
04h  
9Fh  
05h  
03h  
0Bh  
0Ah  
02h  
DBh  
D8h  
B9h  
ABh  
0
0
0
0
3
3
3
3
3
3
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Write Disable  
Read Identification  
Read Status Register  
Read Data Bytes  
1 to 3  
1 to  
1 to ∞  
1 to ∞  
1 to 256  
1 to 256  
0
RDSR  
READ  
FAST_READ Read Data Bytes at Higher Speed  
PW  
PP  
Page Write  
Page Program  
PE  
Page Erase  
SE  
Sector Erase  
0
DP  
Deep Power-down  
Release from Deep Power-down  
0
RDP  
0
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