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M25P64-VMF6TP 参数 Datasheet PDF下载

M25P64-VMF6TP图片预览
型号: M25P64-VMF6TP
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位,低电压,串行闪存的50MHz SPI总线接口 [64 Mbit, Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 38 页 / 521 K
品牌: STMICROELECTRONICS [ STMICROELECTRONICS ]
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M25P64
Read Data Bytes (READ)
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte
address (A23-A0), each bit being latched-in during
the rising edge of Serial Clock (C). Then the mem-
ory contents, at that address, is shifted out on Se-
rial Data Output (Q), each bit being shifted out, at
a maximum frequency f
R
, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in
The first byte addressed can be at any location.
The address is automatically incremented to the
next higher address after each byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) instruction.
When the highest address is reached, the address
counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is termi-
nated by driving Chip Select (S) High. Chip Select
(S) can be driven High at any time during data out-
put. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on
the cycle that is in progress.
Figure 14. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
S
0
C
Instruction
24-Bit Address
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
D
High Impedance
Q
23 22 21
MSB
3
2
1
0
Data Out 1
7
6
5
4
3
2
1
0
Data Out 2
7
MSB
AI03748D
Note: 1. Address bit A23 is Don’t Care.
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