M24C16-125 M24C08-125 M24C04-125 M24C02-125
Figure 9. Read mode sequences
Device operation
ACK
NO ACK
Current
Address
Read
Dev select
Data out
R/W
ACK
ACK
ACK
NO ACK
Random
Address
Read
Dev select *
Byte address
Dev select *
Data out
R/W
R/W
ACK
ACK
ACK
NO ACK
Data out N
Sequentila
Current
Read
Dev select
Data out 1
R/W
ACK
ACK
ACK
R/W
ACK
Sequential
Random
Read
Dev select *
Byte address
Dev select *
Data out 1
R/W
ACK
NO ACK
Data out N
AI01942b
1. The seven most significant bits of the device select code of a Random Read (in the 1st and 3rd bytes) must
be identical.
3.7
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
The device has an internal address counter which is incremented each time a byte is read.
3.7.1
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 9) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
Doc ID 022564 Rev 1
17/30
STMICROELECTRONICS [ ST ]
