M24C16-125 M24C08-125 M24C04-125 M24C02-125
Device operation
Figure 6.
Write mode sequences with WC = 1 (data write inhibited)
WC
ACK
ACK
NO ACK
Byte Write
Dev select
Byte address
Data in
R/W
WC
ACK
ACK
NO ACK
NO ACK
Data in 3
Page Write
Dev select
Byte address
Data in 1
Data in 2
R/W
WC (cont'd)
NO ACK
NO ACK
Page Write
(cont'd)
Data in N
AI02803d
3.6
Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7, and waits for an
address byte. The device responds to the address byte with an acknowledge bit, and then
waits for the data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
th
the “10 bit” time slot), either at the end of a Byte Write or a Page Write, the internal write
cycle is triggered. A Stop condition at any other time slot does not trigger the internal write
cycle.
After the Stop condition, the t delay, and the successful completion of a Write operation,
w
the device internal address counter is automatically incremented, to point to the next byte
address after the last one that was modified. During the internal Write cycle,
Serial Data (SDA) is disabled internally, and the device does not respond to any request.
If the Write Control (WC) input is driven High, the Write instruction is not executed and the
corresponding data bytes are not acknowledged as shown in Figure 6.
Doc ID 022564 Rev 1
13/30
STMICROELECTRONICS [ ST ]
