FlashFlex MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
TABLE 14-7: DC Electrical Characteristics for SST89V516RDx
TA = -40°C to +85°C; VDD = 2.7-3.6V; VSS = 0V
Symbol Parameter
Test Conditions
Min
Max
0.7
Units
VIL
Input Low Voltage
2.7 < VDD < 3.6
2.7 < VDD < 3.6
2.7 < VDD < 3.6
VDD = 2.7V
-0.5
V
V
V
VIH
VIH1
VOL
Input High Voltage
0.2VDD + 0.9 VDD + 0.5
Input High Voltage (XTAL1, RST)
Output Low Voltage (Ports 1.5, 1.6, 1.7)
0.7VDD
VDD + 0.5
I
OL = 16mA
1.0
V
VOL
Output Low Voltage (Ports 1, 2, 3)1
VDD = 2.7V
OL = 100µA2
OL = 1.6mA2
OL = 3.5mA2
VDD = 2.7V
OL = 200µA2
I
I
I
0.3
0.45
1.0
V
V
V
VOL1
Output Low Voltage (Port 0, ALE, PSEN#)1,3
I
0.3
V
V
IOL = 3.2mA2
0.45
VOH
Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)4
VDD = 2.7V
I
OH = -10µA
IOH = -30µA
OH = -60µA
VDD - 0.3
VDD - 0.7
VDD - 1.5
V
V
V
I
VOH1
Output High Voltage (Port 0 in External Bus Mode)4
VDD = 2.7V
IOH = -200µA
VDD - 0.3
VDD - 0.7
2.35
V
V
I
OH = -3.2mA
VBOD
IIL
Brown-out Detection Voltage
Logical 0 Input Current (Ports 1, 2, 3)
Logical 1-to-0 Transition Current (Ports 1, 2, 3)5
Input Leakage Current (Port 0)
RST Pull-down Resistor
Pin Capacitance6
2.55
-75
-650
10
V
VIN = 0.4V
VIN = 2V
µA
µA
µA
KΩ
pF
ITL
ILI
0.45 < VIN < VDD-0.3
RRST
CIO
IDD
225
15
@ 1 MHz, 25°C
Power Supply Current
IAP Mode
@ 33 MHz
47
30
mA
mA
Active Mode
@ 33 MHz
Idle Mode
@ 33 MHz
21
45
55
mA
µA
Power-down Mode (min. VDD = 2V)
TA = 0°C to +70°C
TA = -40°C to +85°C
µA
T14-7.1 1273
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
Maximum IOL per 8-bit port:
15mA
26mA
Maximum IOL total for all outputs: 71mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the
listed test conditions.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 & 3. The noise
due to external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. In
the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to
qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
3. Load capacitance for Port 0, ALE & PSEN#= 100pF, load capacitance for all other outputs = 80pF.
©2007 Silicon Storage Technology, Inc.
S71273-03-000
1/07
67
SST [ SILICON STORAGE TECHNOLOGY, INC ]
