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SST89E516RD2-40-C-NJE 参数 Datasheet PDF下载

SST89E516RD2-40-C-NJE图片预览
型号: SST89E516RD2-40-C-NJE
PDF下载: 下载PDF文件 查看货源
内容描述: FlashFlex MCU [FlashFlex MCU]
分类和应用: 外围集成电路微控制器PC时钟
文件页数/大小: 81 页 / 832 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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FlashFlex MCU  
SST89E516RD2 / SST89E516RD  
SST89V516RD2 / SST89V516RD  
Data Sheet  
14.2 AC Electrical Characteristics  
AC Characteristics: (Over Operating Conditions: Load Capacitance for Port 0, ALE#, and PSEN# = 100pF;  
Load Capacitance for All Other Outputs = 80pF)  
TABLE 14-8: AC Electrical Characteristics (1 of 2)  
TA = -40°C to +85°C, VDD = 2.7-3.6V@33MHz, 4.5-5.5V@40MHz, VSS = 0V  
Oscillator  
33 MHz (x1 Mode)  
40 MHz (x1 Mode)  
16 MHz (x2 Mode)1 20 MHz (x2 Mode)1  
Variable  
Symbol  
Parameter  
Min  
0
Max  
33  
Min  
0
Max  
40  
Min  
Max  
40  
Units  
MHz  
MHz  
ns  
0
1/TCLCL  
x1 Mode Oscillator Frequency  
0
16  
0
20  
0
20  
1/2TCLCL x2 Mode Oscillator Frequency  
46  
5
35  
2TCLCL - 15  
TLHLL  
TAVLL  
ALE Pulse Width  
TCLCL - 25 (3V)  
TCLCL - 15 (5V)  
TCLCL - 25 (3V)  
TCLCL - 15 (5V)  
ns  
Address Valid to ALE Low  
10  
10  
ns  
5
ns  
TLLAX  
TLLIV  
TLLPL  
Address Hold After ALE Low  
ALE Low to Valid Instr In  
ALE Low to PSEN# Low  
ns  
56  
4TCLCL - 65 (3V)  
4TCLCL - 45 (5V)  
ns  
55  
ns  
5
TCLCL - 25 (3V)  
TCLCL - 15 (5V)  
ns  
10  
60  
ns  
66  
3TCLCL - 25 (3V)  
3TCLCL - 15 (5V)  
ns  
TPLPH  
TPLIV  
PSEN# Pulse Width  
35  
25  
3TCLCL - 55 (3V)  
3TCLCL - 50 (5V)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
PSEN# Low to Valid Instr In  
25  
10  
0
TPXIX  
TPXIZ  
Input Instr Hold After PSEN#  
Input Instr Float After PSEN#  
TCLCL - 5 (3V)  
TCLCL - 15 (5V)  
22  
17  
TCLCL - 8  
TPXAV  
TAVIV  
PSEN# to Address valid  
Address to Valid Instr In  
72  
10  
5TCLCL - 80 (3V)  
5TCLCL - 60 (5V)  
10  
65  
10  
TPLAZ  
TRLRH  
PSEN# Low to Address Float  
RD# Pulse Width  
142  
142  
6TCLCL - 40 (3V)  
6TCLCL - 30 (5V)  
120  
120  
6TCLCL - 40 (3V)  
6TCLCL - 30 (5V)  
ns  
TWLWH  
TRLDV  
Write Pulse Width (WE#)  
RD# Low to Valid Data In  
62  
5TCLCL - 90 (3V)  
5TCLCL - 50 (5V)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
75  
0
0
0
TRHDX  
TRHDZ  
Data Hold After RD#  
Data Float After RD#  
36  
2TCLCL - 25 (3V)  
2TCLCL - 12 (5V)  
8TCLCL - 90 (3V)  
8TCLCL - 50 (5V)  
9TCLCL - 90 (3V)  
9TCLCL - 75 (5V)  
38  
152  
183  
116  
TLLDV  
TAVDV  
TLLWL  
TAVWL  
ALE Low to Valid Data In  
Address to Valid Data In  
150  
150  
90  
66  
46  
3TCLCL - 25 (3V) 3TCLCL + 25 (3V)  
3TCLCL - 15 (5V) 3TCLCL + 15 (5V)  
ALE Low to RD# or WR# Low  
Address to RD# or WR# Low  
60  
70  
4TCLCL - 75 (3V)  
4TCLCL - 30 (5V)  
ns  
ns  
©2007 Silicon Storage Technology, Inc.  
S71273-03-000  
1/07  
70  
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