FlashFlex MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
TABLE 14-3: AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . . 10 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF
See Figures 14-8 and 14-10
T14-3.0 1273
TABLE 14-4: Recommended System Power-up Timings
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
1
TPU-WRITE
100
µs
T14-4.0 1273
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter
TABLE 14-5: Pin Impedance (VDD=3.3V, TA=25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
Pin Inductance
15 pF
12 pF
20 nH
1
CIN
VIN = 0V
2
LPIN
T14-5.0 1273
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. Refer to PCI spec.
©2007 Silicon Storage Technology, Inc.
S71273-03-000
1/07
64
SST [ SILICON STORAGE TECHNOLOGY, INC ]
