32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Data Sheet
ADDRESSES
T
CE
CE#
OE#
WE#
T
OE
T
OEH
T
BR
DQ
6
VALID DATA
TWO READ CYCLES
1270 F07.0
WITH SAME OUTPUTS
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
555 555 2AA
555
2AA
555
ADDRESSES
CE#
OE#
T
WP
WE#
T
T
BR
BY
RY/BY#
DQ
XXAA
XX55
XX80
XXAA
XX55
XX10
15-0
VALID
1270 F08.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals
are interchageable as long as minimum timings are met. (See Table 16)
X can be V or V , but no other value.
IL IH
FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
21
SST [ SILICON STORAGE TECHNOLOGY, INC ]
