64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Data Sheet
32-KByte and 64-KByte Block-Erase
The 32-KByte Block-Erase instruction clears all bits in the
selected 32 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. The
64-KByte Block-Erase instruction clears all bits in the
selected 64 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. Prior to
any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the
duration of any command sequence. The 32-Kbyte Block-
Erase instruction is initiated by executing an 8-bit com-
mand, 52H, followed by address bits A23-A0. Address bits
determine block address (BAX), remaining address bits can
be VIL or VIH. CE# must be driven high before the instruction
is executed. The 64-Kbyte Block-Erase instruction is initi-
ated by executing an 8-bit command D8H, followed by
address bits A23-A0. Address bits AMS-A15 are used to
determine block address (BAX), remaining address bits can
be VIL or VIH. CE# must be driven high before the instruction
is executed. Poll the Busy bit in the software status register
or wait TBE for the completion of the internal self-timed 32-
KByte Block-Erase or 64-KByte Block-Erase cycles. See
Figure 13 for the 32-KByte Block-Erase sequence and Fig-
ure 14 for the 64-KByte Block-Erase sequence.
AMS-A15 (AMS = Most Significant Address) are used to
CE#
SCK
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
15 16
23
31
24
52
ADDR
MSB
ADDR ADDR
SI
MSB
HIGH IMPEDANCE
SO
1392 F32.0
FIGURE 13: 32-KByte Block-Erase Sequence
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
24
MODE 0
SCK
D8
ADDR
MSB
ADDR
ADDR
SI
MSB
HIGH IMPEDANCE
SO
1327 F33.0
FIGURE 14: 64-KByte Block-Erase Sequence
©2010 Silicon Storage Technology, Inc.
S71392-04-000
04/10
16
SST [ SILICON STORAGE TECHNOLOGY, INC ]
