64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Data Sheet
Dual-Input Page-Program (50 MHz)
Dual-Input Page-Program instruction A2H, doubles the
data input transfer of normal Page-Program instruction and
supports up to 50MHz. Data to be programmed is entered
using two I/O pins, SIO1 and SIO0. Prior to the program
operation the Write-Enable (WREN) instruction must be
executed. The Dual-Input Page-Program instruction is
entered by driving CE# low, followed by the instruction
code, A2H, three address bytes, and at least one data byte
on serial data inputs SIO1 and SIO0 pins. CE# must be
driven low for the entire duration of the sequence. The
Dual-Input Page-Program instruction programs up to 256
bytes of data in the memory. The selected page address
must be in the erased state (FFH) before initiating the
Page-Program operation. A Dual-Input Page-Program
applied to a protected memory area will be ignored.
driven high the instruction is executed and the user may
poll the WEL and Busy bit of the software status register or
wait TPP for the completion of the internal self-timed Page-
Program operation. See Figure 10 for the Dual-Input-Page-
Program sequence.
For Dual-Input Page-Program, the memory range for the
SST25VF064C is set in 256 byte page boundaries. The
device handles shifting of more than 256 bytes of data by
keeping the last 256 bytes of data shifted as the correct
data to be programmed. If the target address for the Page-
Program instruction is not the beginning of the page bound-
ary (A7-A0 are not all zero) and the number of data input
exceeds or overlaps the end of the address of the page
boundary, the excess data inputs will wrap around and will
be programmed at the start of that target page.
CE# must be driven high after the seventh and eight bit of
the last data byte has been latched; otherwise, the dual
input program instruction is not executed. Once CE# is
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 28 39 40 41 42 43 44 45 46 47
SCK
24-bit Address (1)
23 22 21
SIO
SIO
0
A2
3
2
1
0
6
7
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4
Data Byte 256
High Impedance
1
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
MSB
MSB
MSB
MSB
MSB
1392 F31.0
FIGURE 11: Dual-Input Page-Program
©2010 Silicon Storage Technology, Inc.
S71392-04-000
04/10
14
SST [ SILICON STORAGE TECHNOLOGY, INC ]
