16 Mbit SPI Serial Flash
SST25VF016B
A Microchip Technology Company
Data Sheet
32-KByte and 64-KByte Block-Erase
The 32-KByte Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-
Erase instruction applied to a protected memory area will be ignored. The 64-KByte Block-Erase instruc-
tion clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected mem-
ory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed.
CE# must remain active low for the duration of any command sequence. The 32-Kbyte Block-Erase
instruction is initiated by executing an 8-bit command, 52H, followed by address bits [A23-A0]. Address
bits [AMS-A15] (AMS = Most Significant Address) are used to determine block address (BAX), remaining
address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. The 64-Kbyte Block-
Erase instruction is initiated by executing an 8-bit command D8H, followed by address bits [A23-A0]. Address bits
[AMS-A15] are used to determine block address (BAX), remaining address bits can be VIL or VIH. CE# must be
driven high before the instruction is executed. The user may poll the Busy bit in the software status register or
wait TBE for the completion of the internal self-timed 32-KByte Block-Erase or 64-KByte Block-Erase
cycles. See Figures 13 and 14 for the 32-KByte Block-Erase and 64-KByte Block-Erase sequences.
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
24
MODE 0
SCK
52
ADDR
MSB
ADDR ADDR
SI
MSB
HIGH IMPEDANCE
SO
1271 32KBklEr.0
Figure 13:32-KByte Block-Erase Sequence
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
24
MODE 0
SCK
D8
ADDR
MSB
ADDR
ADDR
SI
MSB
HIGH IMPEDANCE
SO
1271 63KBlkEr.0
Figure 14:64-KByte Block-Erase Sequence
©2011 Silicon Storage Technology, Inc.
S71271-04-000
01/11
16
SST [ SILICON STORAGE TECHNOLOGY, INC ]
