16 Mbit SPI Serial Flash
SST25VF016B
A Microchip Technology Company
Data Sheet
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored
if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence.
The Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven
high before the instruction is executed. The user may poll the Busy bit in the software status register or wait
TCE for the completion of the internal self-timed Chip-Erase cycle. See Figure 15 for the Chip-Erase
sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
MODE 0
SCK
60 or C7
SI
MSB
HIGH IMPEDANCE
SO
1271 ChEr.0
Figure 15:Chip-Erase Sequence
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register
may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in
progress, the Busy bit may be checked before sending any new commands to assure that the new
commands are properly received by the device. CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing
clock cycles until it is terminated by a low to high transition of the CE#. See Figure 16 for the RDSR
instruction sequence.
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK
SI
05
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
Status
Register Out
1271 RDSRseq.0
Figure 16:Read-Status-Register (RDSR) Sequence
©2011 Silicon Storage Technology, Inc.
S71271-04-000
01/11
17
SST [ SILICON STORAGE TECHNOLOGY, INC ]
