FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
Preliminary Specifications
The Prog-SB1, Prog-SB2, Prog-SB3 commands program
the security bits, the functions of these bits are described in
the Security Lock section and also in Table 9-1. Once pro-
grammed, these bits can only be erased through a Chip-
Erase command. See Figure 14-21 for timing waveforms.
4.1.6 Instructions to Perform External Host Mode
Commands
To program data into the memory array, apply power
supply voltage (VDD) to VDD and RST pins, and per-
form the following steps:
Prog-SC0 command programs SC0 bit, which determines
the state of SFCF[0] out of reset. Once programmed, SC0
can only be restored to an erased state via a Chip-Erase
command. See Figure 14-22 for timing waveforms.
1. Maintain RST high and set PSEN# from logic high
to low, in sequence according to the appropriate
timing diagram.
2. Raise EA# High (VIH).
Prog-SC1 command programs SC1 bit, which determines
the state of SFCF[1] out of reset. Once programmed, SC1
can only be restored to an erased state via a Chip-Erase
command. See Figure 14-22 for timing waveforms.
3. Issue Read-ID command to enable the external
host mode.
4. Verify that the memory blocks or sectors for pro-
gramming is in the erased state, FFH. If they are
not erased, then erase them using the appropriate
Erase command.
4.1.4 External Host Mode Clock Source
In external host mode, an internal oscillator will provide
clocking for the device, and the oscillator is unaffected by
the clock doubler logic. The on-chip oscillator will be turned
on as the device enters external host mode; i.e. when
PSEN# goes low while RST is high. During external host
mode, the CPU core is held in reset. Upon exit from exter-
nal host mode, the internal oscillator is turned off.
5. Select the memory location using the address
lines (P3[5:4], P2[5:0], P1[7:0]).
6. Present the data in on P0[7:0].
7. Pulse ALE/PROG#, observing minimum pulse
width.
4.1.5 Flash Operation Status Detection Via External
Host Handshake
8. Wait for low to high transition on Ready/Busy#
(P3[3]).
The device provides two methods for an external host to
detect the completion of a flash memory operation to opti-
mize the Program or Erase time. The end of a flash mem-
ory operation cycle can be detected by:
9. Repeat steps 5 - 8 until programming is finished.
10. Verify the flash memory contents.
4.1.7 Additional Read Commands in External Host
Mode
1. monitoring the Ready/Busy# bit at P3[3];
2. monitoring the Data# Polling bit at P0[3].
The procedure to issue additional read commands, shown
in Table 4-4 below, is the same as the read ID command
format, only the address is changed. Here is a short list of
useful features:
4.1.5.1 Ready/Busy# (P3[3])
The progress of the flash memory programming can be
monitored by the Ready/Busy# output signal. P3[3] is
driven low, some time after ALE/PROG# goes low during a
flash memory operation to indicate the Busy# status of the
Flash Control Unit (FCU). P3[3] is driven high when the
flash programming operation is completed to indicate the
ready status.
•
Read the status of the security bits
(SB1_i, SB2_i, SB3_i).
•
•
Read the configuration bits (SC0_i, SC1_i) status.
Read the clock mode (EDC_i) status.
Note: Commands shown in Table 4-4 are not the
ARMING type.
4.1.5.2 Data# Polling (P0[3])
During a Program operation, any attempts to read (Byte-
Verify), while the device is busy, will receive the comple-
ment of the data of the last byte loaded (logic low, i.e. “0” for
an Erase) on P0[3] with the rest of the bits “0”. During a
Program operation, the Byte-Verify command is reading
the data of the last byte loaded, not the data at the address
specified.
©2004 Silicon Storage Technology, Inc.
S71255-00-000
3/04
38
SST [ SILICON STORAGE TECHNOLOGY, INC ]
