FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
Preliminary Specifications
4.0 FLASH MEMORY PROGRAMMING
The device internal flash memory can be programmed or
erased using the following two methods:
logic high to a logic low while RST input is being held con-
tinuously high. The device will stay in external host mode
as long as RST = 1 and PSEN# = 0.
•
•
External Host Programming mode
A Read-ID operation is necessary to “arm” the device in
external host mode, and no other external host mode com-
mands can be enabled until a Read-ID is performed. In
external host mode, the internal flash memory blocks are
accessed through the re-assigned I/O port pins (see Figure
4-1 for details) by an external host, such as a MCU program-
mer, a PCB tester or a PC-controlled development board.
In-Application Programming (IAP) mode
4.1 External Host Programming Mode
External host programming mode allows the user to pro-
gram the flash memory directly without using the CPU.
External host mode is entered by forcing PSEN# from a
TABLE
4-1: EXTERNAL HOST MODE COMMANDS FOR SST89E/V5XRD2
P3[5:4]
PROG#/
ALE
Operation
RST PSEN#
EA# P3[7] P3[6] P2[7] P2[6] P0[7:0] P2[5:0] P1[7:0]
Read-ID
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIH1
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIH
1
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIH
VIH
VIL
VIL
VIH
VIL
VIH
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIL
DO
X
AH
X
AL
X
Chip-Erase
Block-Erase
Sector-Erase
Byte-Program
Byte-Verify (Read)
Prog-SC0
A[15:13]
X
X
X
AH
AH
AH
5AH
AAH
X
AL
AL
AL
X
DI
DO
X
VIH
Prog-SC1
X
X
Prog-SB1
X
X
Prog-SB2
X
X
X
Prog-SB3
X
X
X
Enable-Clock-Double
X
55H
X
T4-1.0 1255
1. Symbol signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input.
All other combinations of the above input pins are invalid and may result in unexpected behaviors.
Note: VIL = Input Low Voltage; VIH = Input High Voltage; VIH1 = Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte;
AH = Address high order byte; DI = Data Input; DO = Data Output; A[15:13] = 0xxb for Block 0 and A[15:13] = 111b for Block 1
©2004 Silicon Storage Technology, Inc.
S71255-00-000
3/04
35
SST [ SILICON STORAGE TECHNOLOGY, INC ]
