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89E52RD2-40-C-NJE 参数 Datasheet PDF下载

89E52RD2-40-C-NJE图片预览
型号: 89E52RD2-40-C-NJE
PDF下载: 下载PDF文件 查看货源
内容描述: 8位8051 Compatibale单片机(MCU)与嵌入式超快闪记忆 [8 bit 8051-Compatibale Microcontroller (MCU) with Embedded SuperFlash Memory]
分类和应用: 微控制器
文件页数/大小: 91 页 / 969 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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FlashFlex51 MCU  
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2  
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2  
Preliminary Specifications  
TABLE  
4-2: EXTERNAL HOST MODE COMMANDS FOR SST89E/V516RD2  
PROG#/  
P3[5:4]  
Operation  
RST PSEN#  
ALE  
EA# P3[7] P3[6] P2[7] P2[6] P0[7:0] P2[5:0] P1[7:0]  
Read-ID  
VIH1  
VIH1  
VIH1  
VIH1  
VIH1  
VIH1  
VIH1  
VIH1  
VIH1  
VIH1  
VIH1  
VIH1  
VIH1  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIH  
1
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
VIL  
VIL  
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
VIL  
VIL  
VIH  
VIL  
VIL  
VIH  
VIL  
VIH  
VIH  
VIL  
VIL  
VIL  
VIH  
VIL  
VIH  
VIL  
VIL  
VIL  
VIL  
VIH  
VIH  
VIL  
VIL  
VIL  
VIL  
VIH  
VIH  
VIL  
VIL  
VIL  
VIH  
VIH  
VIH  
VIL  
VIL  
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
VIL  
DO  
X
AH  
X
AL  
X
Chip-Erase  
Block-Erase  
Sector-Erase  
Byte-Program  
Byte-Verify (Read)  
Select-Block0  
Select-Block1  
Prog-SC0  
X
X
X
X
AH  
AH  
AH  
55H  
A5H  
5AH  
X
AL  
AL  
AL  
X
DI  
DO  
X
VIH  
X
X
X
X
Prog-SB1  
X
X
Prog-SB2  
X
X
X
Prog-SB3  
X
X
X
Enable-Clock-Double  
X
55H  
X
T4-2.0 1255  
1. Symbol signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input. All other combinations  
of the above input pins are invalid and may result in unexpected behaviors.  
Note: VIL = Input Low Voltage; VIH = Input High Voltage; VIH1 = Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte;  
AH = Address high order byte; DI = Data Input; DO = Data Output  
V
V
RST  
SS DD  
Input/  
Output  
Data  
0
Port 0  
6
7
Bus  
0
1
0
1
2
3
4
5
6
7
2
3
4
5
Address Bus  
A -A  
13 8  
Port 2  
Ready/Busy#  
Port 3  
A
A
14  
Address Bus  
6
7
0
Flash  
Control Signals  
A
-A  
15 14  
15  
Flash  
Control Signals  
Address Bus  
Port 1  
6
7
A -A  
7
0
EA# ALE /PSEN#  
PROG#  
1255 F07.0  
FIGURE  
4-1: I/O PIN ASSIGNMENTS FOR EXTERNAL HOST MODE  
©2004 Silicon Storage Technology, Inc.  
S71255-00-000  
3/04  
36  
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