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89E52RD2-40-C-NJE 参数 Datasheet PDF下载

89E52RD2-40-C-NJE图片预览
型号: 89E52RD2-40-C-NJE
PDF下载: 下载PDF文件 查看货源
内容描述: 8位8051 Compatibale单片机(MCU)与嵌入式超快闪记忆 [8 bit 8051-Compatibale Microcontroller (MCU) with Embedded SuperFlash Memory]
分类和应用: 微控制器
文件页数/大小: 91 页 / 969 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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FlashFlex51 MCU  
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2  
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2  
Preliminary Specifications  
Timer/Counter 2 Control Register (T2CON)  
Location  
7
6
5
4
3
2
1
0
Reset Value  
C8H  
TF2  
EXF2  
RCLK  
TCLK  
EXEN2  
TR2  
C/T2#  
CP/RL2#  
00H  
Symbol  
Function  
TF2  
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2  
will not be set when either RCLK or TCLK = 1.  
EXF2  
Timer 2 external flag set when either a capture or reload is caused by a negative  
transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will  
cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by  
software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).  
RCLK  
TCLK  
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for  
its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for  
the receive clock.  
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for  
its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflow to be used for  
the transmit clock.  
EXEN2  
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result  
of a negative transition on T2EX if Timer 2 is not being used to clock the serial port.  
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.  
TR2  
Start/stop control for Timer 2. A logic 1 starts the timer.  
C/T2#  
Timer or counter select (Timer 2)  
0: Internal timer (OSC/6 in 6 clock mode, OSC/12 in 12 clock mode)  
1: External event counter (falling edge triggered)  
CP/RL2#  
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if  
EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or  
negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1,  
this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.  
Timer/Counter 2 Mode Control (T2MOD)  
Location  
7
6
5
4
3
2
1
0
Reset Value  
C9H  
-
-
-
-
-
-
T2OE  
DCEN  
xxxxxx00b  
Symbol  
Function  
-
Not implemented, reserved for future use.  
Note: User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.  
T2OE  
DCEN  
Timer 2 Output Enable bit.  
Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down  
counter.  
©2004 Silicon Storage Technology, Inc.  
S71255-00-000  
3/04  
33  
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