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39VF6401 参数 Datasheet PDF下载

39VF6401图片预览
型号: 39VF6401
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位/ 32兆位/ 64兆位( X16 )多用途闪存+ [16 Mbit / 32 Mbit / 64 Mbit (x16) Multi-Purpose Flash Plus]
分类和应用: 闪存
文件页数/大小: 32 页 / 498 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
 浏览型号39VF6401的Datasheet PDF文件第14页浏览型号39VF6401的Datasheet PDF文件第15页浏览型号39VF6401的Datasheet PDF文件第16页浏览型号39VF6401的Datasheet PDF文件第17页浏览型号39VF6401的Datasheet PDF文件第19页浏览型号39VF6401的Datasheet PDF文件第20页浏览型号39VF6401的Datasheet PDF文件第21页浏览型号39VF6401的Datasheet PDF文件第22页  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
T
BE  
SIX-BYTE CODE FOR BLOCK-ERASE  
5555 5555 2AAA  
5555  
2AAA  
BA  
ADDRESS A  
MS-0  
X
CE#  
OE#  
WE#  
T
WP  
DQ  
15-0  
XXAA  
SW0  
XX55  
SW1  
XX80  
SW2  
XXAA  
SW3  
XX55  
SW4  
XX50  
SW5  
1223 F09.4  
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are  
interchageable as long as minimum timings are met. (See Table 17)  
BA = Block Address  
X
A
A
= Most significant address  
MS  
MS  
= A for SST39VF1601/1602, A for SST39VF3201/3202, and A for SST39VF6401/6402  
19 20 21  
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence  
IL IH  
X can be V or V but no other value  
IL IH,  
FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM  
T
SE  
SIX-BYTE CODE FOR SECTOR-ERASE  
5555  
2AAA  
5555  
5555  
2AAA  
SA  
ADDRESS A  
X
MS-0  
CE#  
OE#  
WE#  
T
WP  
DQ  
XXAA  
SW0  
XX55  
SW1  
XX80  
SW2  
XXAA  
SW3  
XX55  
SW4  
XX30  
SW5  
15-0  
1223 F10.4  
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are  
interchageable as long as minimum timings are met. (See Table 17)  
SA = Sector Address  
X
A
MS  
A
MS  
= Most significant address  
= A for SST39VF1601/1602, A for SST39VF3201/3202, and A for SST39VF6401/6402  
19  
20  
21  
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence  
IL  
IH  
X can be V or V , but no other value  
IL  
IH  
FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
18