欢迎访问ic37.com |
会员登录 免费注册
发布采购

39VF6401 参数 Datasheet PDF下载

39VF6401图片预览
型号: 39VF6401
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位/ 32兆位/ 64兆位( X16 )多用途闪存+ [16 Mbit / 32 Mbit / 64 Mbit (x16) Multi-Purpose Flash Plus]
分类和应用: 闪存
文件页数/大小: 32 页 / 498 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
 浏览型号39VF6401的Datasheet PDF文件第13页浏览型号39VF6401的Datasheet PDF文件第14页浏览型号39VF6401的Datasheet PDF文件第15页浏览型号39VF6401的Datasheet PDF文件第16页浏览型号39VF6401的Datasheet PDF文件第18页浏览型号39VF6401的Datasheet PDF文件第19页浏览型号39VF6401的Datasheet PDF文件第20页浏览型号39VF6401的Datasheet PDF文件第21页  
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
ADDRESS A  
MS-0  
T
CE  
CE#  
OE#  
WE#  
T
OES  
T
T
OE  
OEH  
DQ and DQ  
6
2
TWO READ CYCLES  
WITH SAME OUTPUTS  
1223 F07.3  
Note:  
A
A
= Most significant address  
MS  
= A for SST39VF1601/1602, A for SST39VF3201/3202, and A for SST39VF6401/6402  
MS  
19  
20  
21  
FIGURE 7: TOGGLE BITS TIMING DIAGRAM  
T
SCE  
SIX-BYTE CODE FOR CHIP-ERASE  
5555 5555 2AAA  
5555  
2AAA  
5555  
ADDRESS A  
MS-0  
CE#  
OE#  
T
WP  
WE#  
DQ  
15-0  
XXAA  
SW0  
XX55  
SW1  
XX80  
SW2  
XXAA  
SW3  
XX55  
SW4  
XX10  
SW5  
1223 F08.4  
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are  
interchageable as long as minimum timings are met. (See Table 17)  
A
MS  
A
MS  
= Most significant address  
= A for SST39VF1601/1602, A for SST39VF3201/3202, and A for SST39VF6401/6402  
19  
20  
21  
WP# must be held in proper logic state (V ) 1 µs prior to and 1 µs after the command sequence  
IH  
X can be V or V but no other value  
IH,  
IL  
FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
17