16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
T
T
AA
RC
ADDRESS A
MS-0
CE#
OE#
WE#
T
CE
T
OE
T
T
OHZ
V
OLZ
IH
T
CHZ
T
OH
T
HIGH-Z
CLZ
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
1223 F03.2
Note:
A
A
= Most significant address
MS
= A for SST39VF1601/1602, A for SST39VF3201/3202, and A for SST39VF6401/6402
MS
19
20
21
FIGURE 3: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
WP
WE#
T
T
AS
DS
T
WPH
OE#
CE#
T
CH
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
1223 F04.3
Note:
A
= Most significant address
MS
MS
A
= A for SST39VF1601/1602, A for SST39VF3201/3202, and A for SST39VF6401/6402
19
20 21
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence
IL
IH
X can be V or V but no other value
IH,
IL
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71223-03-000
11/03
15
SST [ SILICON STORAGE TECHNOLOGY, INC ]
