ICS87951I
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VDDA
Power
Input
Analog supply pin.
Feedback input to phase detector for regenerating clocks with
"zero delay". LVCMOS / LVTTL interface levels.
Selects divide value for Bank A output as described in Table 3D.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank B output as described in Table 3D.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank C outputs as described in Table 3D.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank D outputs as described in Table 3D.
LVCMOS / LVTTL interface levels.
2
3
4
5
6
EXT_FB
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
GND
Pullup
Input
Input
Input
Input
Power
Pulldown
Pulldown
Pulldown
Pulldown
7, 13, 17,
21, 25, 29
Power supply ground.
8
9
CLK1
Input
Input
Pullup
Non-inverting differential clock input.
nCLK1
Pulldown Inverting differential clock input.
Active HIGH Master Reset. Active LOW output enable. When logic
HIGH, the internal dividers are reset and the outputs are tri-stated
ꢀHiZꢁ. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
10
MR/nOE
Input
Pulldown
11, 15,
19, 23, 27
12, 14,
VDDO
Power
Output
Output
Output
Output supply pins.
QD4, QD3,
Bank D clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Bank B clock output. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
16, 18, 20 QD2, QD1, QD0
22, 24
26
QC1, QC0
QB
Bank A clock output. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
28
30
QA
Output
Input
CLK0
Pulldown LVCMOS / LVTTL phase detector reference clock input.
Selects between the PLL and the reference clock as the input to the
Pulldown dividers. When HIGH, selects PLL. When LOW, selects the reference
clock. LVCMOS / LVTTL interface levels.
31
32
PLL_SEL
CLK_SEL
Input
Input
Clock select input. When HIGH, selects CLK0. When LOW,
Pulldown
selects CLK1, nCLK1. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
KΩ
KΩ
Ω
CPD
Power Dissipation Capacitance ꢀper outputꢁ
Input Pullup Resistor
VDDA, VDDO = 3.47V
25
51
RPULLUP
RPULLDOWN Input Pulldown Resistor
51
7
ROUT
Output Impedance
5
12
87951AYI
www.icst.com/products/hiperclocks.html
REV.B NOVEMBER 23, 2005
3
SPECTRUM [ SPECTRUM MICROWAVE, INC. ]
