ICS87951I
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position theV_REF in
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87951I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDDA and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin.To achieve optimum jitter performance, power
supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin.
3.3V
VDD
.01μF
.01μF
10Ω
10μF
VDDA
FIGURE 2. POWER SUPPLY FILTERING
87951AYI
www.icst.com/products/hiperclocks.html
REV.B NOVEMBER 23, 2005
8
SPECTRUM [ SPECTRUM MICROWAVE, INC. ]
