W255
Serial Configuration Map
Byte 7: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
• The serial bits will be read by the clock driver in the following
order:
Bit
Pin #
Description
DDR7T, DDR7C
Default
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Bit 7 30, 29
Bit 6 28, 27
Bit 5 21, 22
1
1
1
.
DDR6T, DDR6C
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
DDR5T_SDRAM8,
DDR5C_SDRAM9
• Reserved and unused bits should be programmed to “0.”
• SMBus Address for the W255 is:
Bit 4 19, 20
Bit 3 15,16
Bit 2 10, 11
Bit 1 6, 7
DDR4T_SDRAM6,
DDR4C_SDRAM7
1
1
1
1
1
Table 1.
DDR3T_SDRAM4,
DDR3C_SDRAM5
A6
A5
A4
A3
A2
A1
A0
R/W
DDR2T_SDRAM2,
DDR2C_SDRAM3
1
1
0
1
0
0
1
----
DDR1T_SDRAM0,
DDR1C_SDRAM1
Byte 6: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit 0 4, 5
DDR0T_SDRAM10,
DDR0C_SDRAM11
Bit Pin #
Description
Reserved, drive to 0
Default
Bit 7
Bit 6
Bit 5
Bit 4
–
–
–
1
0
0
0
1
1
1
1
1
Reserved, drive to 0
Reserved, drive to 0
FBOUT
Bit 3 45,44 DDR11T, DDR11C
Bit 2 43, 42 DDR10T, DDR10C
Bit 1 39, 38 DDR9T, DDR9C
Bit 0 34, 33 DDR8T, DDR8C
Rev 1.0,November 25, 2006
Page 3 of 9
SPECTRALINEAR [ SPECTRALINEAR INC ]
