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W255H 参数 Datasheet PDF下载

W255H图片预览
型号: W255H
PDF下载: 下载PDF文件 查看货源
内容描述: 200 MHz的24 -输出缓冲器4 DDR或3 SDRAM DIMM, [200 MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS]
分类和应用: 逻辑集成电路光电二极管驱动动态存储器双倍数据速率
文件页数/大小: 9 页 / 196 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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W255  
200 MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS  
Features  
Functional Description  
• One input to 24 output buffer/driver  
The W255 is a 3.3V/2.5V buffer designed to distribute  
high-speed clocks in PC applications. The part has 24 outputs.  
Designers can configure these outputs to support four unbuf-  
fered DDR DIMMS or to support three unbuffered standard  
SDRAM DIMMs and two DDR DIMMS. The W255 can be used  
in conjunction with the W250 or similar clock synthesizer for  
the VIA Pro 266 chipset.  
• Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS  
• One additional output for feedback  
• SMBus interface for individual output control  
• Low skew outputs (< 100 ps)  
• Supports 266-, 333-, and 400 MHz DDR SDRAM  
• Dedicated pin for power management support  
• Space-saving 48-pin SSOP package  
The W255 also includes an SMBus interface which can enable  
or disable each output clock. On power-up, all output clocks  
are enabled (internal pull up).  
Block Diagram  
Pin Configuration[1]  
FBOUT  
SSOP  
BUF_IN  
DDR0T_SDRAM10  
DDR0C_SDRAM11  
Top View  
1
FBOUT  
VDD3.3_2.5  
GND  
48  
47  
SEL_DDR*  
VDD2.5  
GND  
DDR1T_SDRAM0  
DDR1C_SDRAM1  
2
3
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
4
DDR2T_SDRAM2  
DDR0T_SDRAM10  
DDR2C_SDRAM3 DDR0C_SDRAM11  
DDR11T  
DDR11C  
DDR10T  
DDR10C  
VDD2.5  
GND  
DDR9T  
DDR9C  
VDD2.5  
PWR_DWN#*  
GND  
5
6
DRR1T_SDRAM0  
DDR3T_SDRAM4  
DDR1C_SDRAM1  
7
DDR3C_SDRAM5  
SDATA  
8
VDD3.3_2.5  
DDR4T_SDRAM6  
9
SMBus  
Decoding  
GND  
DDR2T_SDRAM2  
DDR2C_SDRAM3  
DDR4C_SDRAM7  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
DDR5T_SDRAM8  
DDR5C_SDRAM9  
VDD3.3_2.5  
SCLOCK  
BUF_IN  
DDR6T  
GND  
DDR6C  
DDR3T_SDRAM4  
DDR8T  
DDR8C  
DDR7T  
DDR3C_SDRAM5  
DDR7C  
VDD3.3_2.5  
VDD2.5  
GND  
DDR8T  
GND  
DDR4T_SDRAM6  
DDR4C_SDRAM7  
DDR5T_SDRAM8  
DDR5C_SDRAM9  
VDD3.3_2.5  
SDATA  
DDR8C  
DDR7T  
DDR7C  
DDR6T  
DDR6C  
GND  
DDR9T  
DDR9C  
DDR10T  
Power Down Control  
PWR_DWN#  
SCLK  
DDR10C  
Note:  
DDR11T  
1. Internal 100K pull-up resistors present on inputs marked  
with *. Design should not rely solely on internal pull-up resistor  
to set I/O pins HIGH.  
DDR11C  
SEL_DDR  
Rev 1.0, November 25, 2006  
Page 1 of 9  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com