W191
pulse. A transitioning data line during a clock high pulse may
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).
How To Use the Serial Data Interface
Electrical Requirements
Figure 1 illustrates electrical characteristics for the serial
interface bus used with the W191. Devices send data over the
bus with an open drain logic output that can (a) pull the bus
line low, or (b) let the bus default to logic 1. The pull-up resistor
on the bus (both clock and data lines) establish a default logic
1. All bus devices generally have logic inputs to receive data.
A write sequence is initiated by a “Start Bit” as shown in
Figure 3. A “Stop Bit” signifies that a transmission has ended.
As stated previously, the W191 sends an “acknowledge” pulse
after receiving eight data bits in each byte as shown in
Figure 4.
Although the W191 is a receive-only device (no data
write-back capability), it does transmit an “acknowledge” data
pulse after each byte is received. Thus, the SDATA line can
both transmit and receive data.
Sending Data to the W191
The device accepts data once it has detected a valid start bit
and address byte sequence. Device functionality is changed
upon the receipt of each data bit (registers are not double
buffered). Partial transmission is allowed meaning that a trans-
mission can be truncated as soon as the desired data bits are
transmitted (remaining registers will be unmodified). Trans-
mission is truncated with either a stop bit or new start bit
(restart condition).
The pull-up resistor should be sized to meet the rise and fall
times specified in AC parameters, taking into consideration
total bus line capacitance.
Signaling Requirements
As shown in Figure 2, valid data bits are defined as stable logic
0 or 1 condition on the data line during a clock HIGH (logic 1)
VDD
VDD
~ 2k
:
~ 2k:
SERIAL BUS DATA LINE
SERIAL BUS CLOCK LINE
SDCLK
SDATA
SCLOCK
SDATA
CLOCK IN
DATA IN
DATA OUT
CLOCK IN
DATA IN
DATA OUT
N
N
N
CLOCK OUT
CHIP SET
(SERIAL BUS MASTER TRANSMITTER)
CLOCK DEVICE
(SERIAL BUS SLAVE RECEIVER)
Figure 1. Serial Interface Bus Electrical Characteristics
.
Rev 1.0,November 20, 2006
Page 6 of 9
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