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W191H 参数 Datasheet PDF下载

W191H图片预览
型号: W191H
PDF下载: 下载PDF文件 查看货源
内容描述: 偏斜受控SDRAM缓冲区 [Skew Controlled SDRAM Buffer]
分类和应用: 动态存储器
文件页数/大小: 9 页 / 157 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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W191  
Absolute Maximum Ratings[3]  
rating only. Operation of the device at these or any other condi-  
tions above those specified in the operating sections of this  
specification is not implied. Maximum conditions for extended  
periods may affect reliability.  
Stresses greater than those listed in this table may cause  
permanent damage to the device. These represent a stress  
Parameter  
VDDQ3, VIN  
TSTG  
TB  
Description  
Voltage on any pin with respect to GND  
Storage Temperature  
Rating  
Unit  
V
–0.5 to + 7.0  
–65 to + 150  
–55 to + 125  
0 to + 70  
°C  
°C  
°C  
°C  
Ambient Temperature under Bias  
Operating Temperature (Commercial)  
Operating Temperature (Industrial)  
TA  
TA  
–40 to + 85  
DC Electrical Characteristics: TA = 0°C to +70°C (Commercial), VDDQ3 = 3.3V 5%,TA = –40°C to +85°C (Industrial),  
V
DDQ3 = 3.3V 5% [4]  
Parame-  
ter  
Description  
Test Condition  
BUF_IN = 100 MHz  
BUF_IN = 100 MHz  
Min.  
Typ.  
173  
5
Max.  
Unit  
mA  
mA  
IDD  
IDD  
3.3V Supply Current  
3.3V Supply Current in three-state  
Logic Inputs (BUF_IN, OE, SCLOCK, SDATA)  
VIL  
Input Low Voltage  
GND–0.3  
2.0  
0.8  
VDDQ3+0.5  
+5  
V
V
VIH  
Input High Voltage  
IILEAK  
IILEAK  
Input Leakage Current, BUF_IN  
Input Leakage Current[5]  
–5  
µA  
µA  
–20  
+5  
Logic Outputs (SDRAM0:5)  
VOL  
VOH  
IOL  
Output Low Voltage  
Output High Voltage  
Output Low Current  
Output High Current  
IOL = 1 mA  
IOH = –1 mA  
VOL = 1.5V  
VOH = 1.5V  
50  
mV  
V
3.1  
65  
70  
100  
110  
160  
185  
mA  
mA  
IOH  
Pin Capacitance/Inductance  
CIN Input Pin Capacitance (Except BUF_IN)  
5
6
7
pF  
pF  
nH  
COUT  
Output Pin Capacitance  
Input Pin Inductance  
LIN  
Notes:  
3. Multiple supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.  
4. Outputs loaded by 6” 60 transmission lines with 20 pF capacitors.  
5. OE, SCLOCK, and SDATA logic pins have a 250-k: internal pull-up resistor (not CMOS level).  
:
Rev 1.0,November 20, 2006  
Page 4 of 9