W191
Table 2. Data Bytes 0–2 Serial Configuration Map[2]
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
0
1
Data Byte 0 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
7
6
5
4
3
2
1
0
6
--
--
--
--
3
SDRAM2
Clock Output Disable
(Reserved)
Low
--
Active
--
--
--
(Reserved)
--
--
--
--
(Reserved)
--
--
--
(Reserved)
--
SDRAM1
--
Clock Output Disable
(Reserved)
Low
--
Active
--
--
1
SDRAM0
Clock Output Disable
--
--
Data Byte 1 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
7
6
5
4
3
2
1
0
--
15
--
--
Clock Output Disable
Clock Output Disable
Clock Output Disable
(Reserved)
--
Low
--
--
SDRAM5
Active
--
--
--
--
--
--
Active
--
13
--
SDRAM4
Clock Output Disable
(Reserved)
Low
--
--
--
--
--
(Reserved)
--
--
--
(Reserved)
--
--
Data Byte 2 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
7
6
5
4
3
2
1
0
11
--
--
--
--
--
--
--
SDRAM3
Clock Output Disable
(Reserved)
Low
--
Active
--
--
--
--
--
--
--
--
--
--
--
--
--
--
(Reserved)
--
(Reserved)
--
(Reserved)
--
(Reserved)
--
(Reserved)
--
(Reserved)
--
Note:
2. At power up all SDRAM outputs are enabled and active. Program Reserved bits to 0.
Rev 1.0,November 20, 2006
Page 3 of 9
SPECTRALINEAR [ SPECTRALINEAR INC ]
