W191
Skew Controlled SDRAM Buffer
Key Specifications
Features
• Six skew controlled CMOS outputs
• Output skew between any two outputs is less than 150 ps
• SMBus Serial configuration interface
• 2.5 ns to 5 ns propagation delay
Supply Voltages:...................................... VDDQ3 = 3.3V 5ꢀ
Operating Temperature: (Commercial) ............. 0°C to +70°C
Operating Temperature: (Industrial).............. –40°C to +85°C
Input Threshold:...................................................1.5V typical
Maximum Input Voltage: .................................. VDDQ3 + 0.5V
Input Frequency: (Commercial) ........................0 to 133 MHz
Input Frequency: (Industrial).............................0 to 100 MHz
BUF_IN to SDRAM0:5 Propagation Delay:.......2.5 ns to 5 ns
Min. Output Edge Rate: .............................................1.0V/ns
Max. Output Skew: ..................................................... 150 ps
Output Duty Cycle:...................................45/55ꢀ worst case
Output Impedance: ...................................................15:typ.
• DC to 133 MHz operation (Commercial)
• DC to 100 MHz operation (Industrial)
• Single 3.3V supply voltage
• Low power CMOS design packaged in a 16-pin SSOP
(Small Shrink Outline Package)
Pin Configuration[1]
Block Diagram
SDATA
SDRAM0
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDQ3
SDRAM5
GND
SMBus
Device Control
SCLOCK
SDRAM1
BUF_IN
GND
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM4
VDDQ3
SDRAM3
GND
BUF_IN
SDRAM2
VDDQ3
SDATA
SCLK
Note:
1. Internal pull-up resistor of 250K on SDATA and SCLK.
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Page 1 of 9
Tel:(408) 855-0555 Fax:(408) 855-0550
www.SpectraLinear.com