CY2SSTU32866
AC Timing Specifications (continued)
Parameter
TPLH
Description
Conditions
Min.
1.2
1
Max.
3
Unit
ns
Propagation Delay from Low to High
Propagation Delay from Low to High
Propagation Delay from Low to High
Propagation Delay from High to Low
Slew Rate Rising
From CK, CK# crossing to
QERR#
TPHL
TrPLH
TrPHL
SLR
2.4
ns
RESET# LOW to QERR# HIGH
RESET# LOW to Q, PPO LOW
dv/dt_r (20 to 80%)
3 (typical)
ns
3
4
4
1
ns
1
1
–
V/ns
V/ns
V/ns
Slew Rate Falling
dv/dt_f (20 to 80%)
dv/dt '
Delta between Rising/Falling Rates
VDD
DUT
RL = 1000:
Test Point
RL = 1000:
TL = 350ps, 50:
CK
CK
CK Inputs
OUT
Test Point
CL = 30pF
RL = 100:
Test Point
C
includes probe and jig capacitance
L
Figure 13. Test Load for Timing Measurements #1
LVCMOS
RESET
VDD
V
DD/2
VDD/2
tinact
0V
tact
IDD
90%
10%
I
tested with clock and data inputs held at V or GND, and I = 0mA
DD O
DD
Figure 14. Active and Inactive Times
tw
V
IH
V
Input
V
ICR
V
ICR
ID
V
IL
V
V
V
= 600mV
ID
= V
= V
+ 250mV (AC Voltage levels) for differential inputs. V = V for LVCMOS inputs.
IH DD
IH
IL
REF
- 250mV ( AC voltage levels) for differential inputs. V = V for LVCMOS inputs
DD
REF
IL
Figure 15. Pulse Duration
Rev 1.0,November 25, 2006
Page 19 of 24
SPECTRALINEAR [ SPECTRALINEAR INC ]
