CY2SSTU32866
DC Electrical Specifications (continued)
Parameter
Description
Conditions
Min.
Max.
Unit
IDDD
Power Supply Current
Dynamic Operating Clock CK# switching 50% duty cycle,
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
28 (typical)
18 (typical)
36 (typical)
27 (typical)
2 (typical)
PA/MHz
Only
VDD = 1.8V
Dynamic Operating per
each Data Input
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CK# switching 50% duty cycle,
PA/MHz
PA/MHz
PA/MHz
PA/MHz
VDD = 1.8V, 1 IO switching 1:1 configuration
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CK# switching 50% duty cycle,
VDD = 1.8V, 1 IO switching 1:2 configuration
Low Power Active Mode, RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CLK only CK# switching 50% duty cycle,
DD = 1.8V, CS Enabled
V
Low Power Active Mode RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
per each Data Input
CK# switching 50% duty cycle,
DD = 1.8V, 1 IO switching 1:1 configuration,
CS Enabled
V
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CK# switching 50% duty cycle,
VDD = 1.8V, 1 IO switching 1:2 configuration;
CS Enabled
2 (typical)
PA/MHz
CIN
Ci (Data and CSR#)
Ci (CK and CK#)
Ci (RESET#)
VI = VREF 250mV
2.5
2
3.5
3
pF
pF
pF
V
IX = 0.9V, VID = 600 mV
VI = VDD or GND
2.5
AC Timing Specifications
Parameter
Description
Clock Frequency
Pulse Duration
Conditions
Min.
–
Max.
Unit
MHz
ns
FCLK
TW
500
–
CK, CK# H or L
1
[4]
TACT
Differential Input Active time
Differential Input Inactive time
Set-up Time
–
10
15
–
ns
[5]
TINACT
TSU
–
ns
DSR# before crossing CK,CK#,
CSR = H
0.7
ns
CSR# before crossing CK,CK#,
DCS = H
0.7
0.5
0.5
–
–
–
ns
ns
ns
DCS# before crossing CK,CK#,
CSR = L
DODT, DCKE and data before
crossing CK,CK#, CK going
HIGH
PAR_IN after crossing CK,CK#
0.5
0.5
ns
ns
TH
Hold Time
DCS#, DODT, DCKE and data
after crossing CK, CK#
–
PAR_IN after crossing CK, CK#
0.5
–
ns
ns
ns
TPDM
Propagation Delay single bit switching From CK, CK# crossing to Q
1.86
1.87
TPDMSS
Propagation Delay simultaneous
switching
From CK, CK# to Q -
simultaneous switching
TPD
Propagation Delay from Low to High
From CK, CK# crossing to PPO
2.15 (typical)
ns
Notes:
4. Data and V
5. Data, V
REF
inputs must be low a minimum time of T max, after RESET# is taken HIGH.
and clock inputs must be held at valid levels (not floating) a minimum time of T
REF
ACT
max after RESET# is taken LOW.
INACT
Rev 1.0,November 25, 2006
Page 18 of 24
SPECTRALINEAR [ SPECTRALINEAR INC ]
