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CY28800 参数 Datasheet PDF下载

CY28800图片预览
型号: CY28800
PDF下载: 下载PDF文件 查看货源
内容描述: 100 - MHz差分缓冲器,用于PCI Express和SATA [100-MHz Differential Buffer for PCI Express and SATA]
分类和应用: PC
文件页数/大小: 15 页 / 211 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28800  
glitches, frequency shifting or amplitude abnormalities among  
others.  
OE_INV Clarification  
The OE_INV pin is an input strap sampled at power-on. The  
functionality of this input is to set the active level polarities for  
OE_[7:0], PWRDWN, and SRC_STP input pins. ‘Active High’  
indicates the functionality of the input is asserted when the  
input voltage level at the pin is high and deasserted when the  
voltage level at the input is low. ‘Active Low’ indicates that the  
functionality of the input is asserted when the voltage level at  
the input is low and deasserted when the voltage level at the  
input pin is high. See VIH and VIL in the DC Electrical Specifi-  
cations for input voltage high and low ranges.  
OE_INV  
PWRDWN  
Mode  
Power Down  
Normal  
0
0
1
1
0
1
0
1
Normal  
Power Down  
PWRDWN Assertion  
When the power down pin is sampled as being asserted by  
two consecutive rising edges of DIFC, all DIFT outputs will be  
held high or Tri-stated (depending on the state of the control  
register drive mode and OE bits) on the next DIFC high to low  
transition. When the SMBus PWRDWN Drive Mode bit is  
programmed to ‘0’, all clock outputs will be held with the DIFT  
pin driven high at 2 x Iref and DIFC tri-stated. However, if the  
control register PWRDWN Drive Mode bit is programmed to  
‘1’, then both DIFT and the DIFC are Tri-stated.  
OE_INV  
PWRDWN  
Active Low  
Active High  
SRC  
OE_[7:0]  
Active High  
Active Low  
0
1
Active Low  
Active High  
PWRDWN Clarification  
The PWRDWN pin is an asynchronous input used to shut off  
all clocks cleanly and instruct the device to evoke power  
savings mode. It may be active high or active low depending  
on the strapped value of the OE_INV input. The PWRDWN pin  
should be asserted prior to shutting off the input clock or power  
to ensure all clocks shut down in a glitch-free manner. This  
signal is synchronized internal to the device prior to powering  
down the clock buffer. PWRDWN is an asynchronous input for  
powering up the system. When the PWRDWN pin is asserted,  
all clocks will be held high or tri-stated (depending on the state  
of the control register drive mode and OE bits) prior to turning  
off the VCO. All clocks will start and stop without any abnormal  
behavior and meet all AC and DC parameters. This means no  
PWRDWN Deassertion  
The power-up latency is less than 1 ms. This is the time from  
the deassertion of the PWRDWN pin or the ramping of the  
power supply or the time from valid SRC_IN input clocks until  
the time that stable clocks are output from the buffer chip (PLL  
locked). IF the control register PWRDWN Drive Mode bit is  
programmed to ‘1’, all differential outputs must be driven high  
in less than 300 Ps of the power down pin deassertion to a  
voltage greater than 200 mV.  
PWRDWN  
DIFT  
DIFC  
Figure 1. PWRDWN Assertion Diagram, OE_INV = 0  
PWRDWN  
DIFT  
DIFC  
Figure 2. PWRDWN Assertion Diagram, OE_INV = 1  
Tstable  
<1 ms  
PWRDWN  
DIFT  
DIFC  
Tdrive_Pwrdwn#  
<300 Ps, >200 mV  
Figure 3. PWRDWN Deassertion Diagram, OE_INV = 0  
Rev 1.0,November 21, 2006  
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