CY28800
Pin Description
Pin
Name
Type
Description
4,5
SRCT_IN, SRCC_IN
I,DIF 0.7V Differential inputs
8,9;12,13;16,17;20,21; 30,29; DIF[T/C][7:0]
34,33;38,37;42,41
O,DIF 0.7V Differential Clock Outputs
6,7,14,15,35,36,43,44
OE_[7:0]
I,SE 3.3V LVTTL input for enabling differential outputs
Active High if OE_INV = 0
Active Low if OE_INV = 1
28
45
26
HIGH_BW#
LOCK
I,SE 3.3V LVTTL input for selecting PLL bandwidth
0 = High BW, 1 = Low BW
O,SE 3.3V LVTTL output, transitions high when PL lock is
achieved (latched output)
PWRDWN
I,SE 3.3V LVTTL input for Power Down
Active Low if OE_INV = 0
Active High if OE_INV = 1
1
SRC_DIV2#
SRC_STP
I,SE 3.3V LVTTL input for selecting input frequency divided by
two, active low
27
I,SE 3.3V LVTTL input for SRC_STP. Disables stoppable outputs.
Active Low if OE_INV = 0
Active High if OE_INV = 1
23
24
46
SCLK
SDATA
IREF
I,SE SMBus Slave Clock Input
I/O,OC Open collector SMBus data
I
A precision resistor is attached to this pin to set the differ-
ential output current
22
PLL/BYPASS#
VDD_A
VSS_A
VSS
I
3.3V LVTTL input for selecting fan-out or PLL operation
48
PWR 3.3V Power Supply for PLL
GND Ground for PLL
47
3,10,18,25,32
2,11,19,31,39
40
GND Ground for outputs
VDD
PWR 3.3V power supply for outputs
OE_INV
I, SE Input strap for setting polarity of OE_[7:0], SRC_STP, and
PWRDWN
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock buffer, a
two-signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, can be individually enabled or disabled. The
registers associated with the Serial Data Interface initializes to
their default setting upon power-up, and therefore use of this
interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for
power management functions.
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11011100 (DCh).
Table 1. Command Code Definition
Bit
Description
7
0 = Block read or block write operation
1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Rev 1.0,November 21, 2006
Page 2 of 15
SPECTRALINEAR [ SPECTRALINEAR INC ]
