CY28800
Byte 2: Control Register 2 (continued)
Bit
@pup
Name
Description
4
0
SRC_STP_DIF[T/C]4
Allow Control DIF[T/C]4 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
3
2
1
0
0
0
0
0
SRC_STP_DIF[T/C]3
SRC_STP_DIF[T/C]2
SRC_STP_DIF[T/C]1
SRC_STP_DIF[T/C]0
Allow Control DIF[T/C]3 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Allow Control DIF[T/C]2 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Allow Control DIF[T/C]1 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Allow Control DIF[T/C]0 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Byte 3: Control Register 3
Bit
7
@pup
Name
Description
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6
5
4
3
2
1
0
Byte 4: Vendor ID Register
Bit
7
@Pup
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
0
0
0
0
1
0
0
0
6
5
4
3
2
Vendor ID Bit 2
1
Vendor ID Bit 1
0
Vendor ID Bit 0
Byte 5: Control Register 5
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6
5
4
3
2
1
0
Rev 1.0,November 21, 2006
Page 5 of 15
SPECTRALINEAR [ SPECTRALINEAR INC ]
