CY28800
SRC_STP Assertion
SRC_STP Deassertion
The impact of asserting the SRC_STP pin is that all DIF
outputs that are set in the control registers to stoppable via
assertion of SRC_STP are stopped after their next transition.
When the control register SRC_STP three-state bit is
programmed to ‘0’, the final state of all stopped DIFT/C signals
is DIFT clock = High and DIFC = Low. There will be no change
to the output drive current values, DIFT will be driven high with
a current value equal 6 x Iref, and DIFC will not be driven.
When the control register SRC_STP three-state bit is
programmed to ‘1’, the final state of all stopped DIF signals is
low, both DIFT clock and DIFC clock outputs will not be driven.
All differential outputs that were stopped will resume normal
operation in a glitch-free manner. The maximum latency from
the deassertion to active outputs is between 2-6 DIFT/C clock
periods (2 clocks are shown) with all DIFT/C outputs resuming
simultaneously. If the control register tri-state bit is
programmed to ‘1’ (tri-state), then all stopped DIFT outputs will
be driven high within 15 ns of SRC_STP deassertion to a
voltage greater than 200 mV.
1 ms
SRC_STP
PWRDWN
DIFT(Free Running
DIFC(Free Running
DIFT (Stoppable)
DIFC (Stoppable)
Figure 6. SRC_STP = Driven, PWRDWN = Driven, OE_INV = 0
1 ms
SRC_STP
PWRDWN
DIFT(Free Running
DIFC(Free Running
DIFT (Stoppable)
DIFC (Stoppable)
Figure 7. SRC_STP = Tri-state, PWRDWN = Driven, OE_INV = 0
1 ms
SRC_STP
PWRDWN
DIFT(Free Running
DIFC(Free Running
DIFT (Stoppable)
DIFC (Stoppable)
Figure 8. SRC_STP = Tri-state, PWRDWN = Tri-state, OE_INV = 0
Rev 1.0,November 21, 2006
Page 8 of 15
SPECTRALINEAR [ SPECTRALINEAR INC ]
