CY28800
Byte 0: Control Register 0
Bit
@pup
Name
Description
7
0
PWRDWN Drive Mode
Power Down drive mode
0 = Driven when stopped, 1 = Tri-state
6
0
SRC_STP Drive Mode
SRC Stop drive mode
0 = Driven when stopped, 1 = Tri-state
5
4
3
2
0
0
0
1
Reserved
Reserved
Reserved
HIGH_BW#
Reserved
Reserved
Reserved
HIGH_BW#
0 = High Bandwidth, 1 = Low bandwidth
1
0
1
1
PLL/BYPASS#
SRC_DIV2#
PLL/BYPASS#
0 = Fanout buffer, 1 = PLL mode
SRC_DIV2# configures output frequency at half the input frequency
0 = Divided by 2 mode (output = input/2),1 = Normal (output = input)
Byte 1: Control Register 1
Bit
@pup
Name
Description
7
1
OE_7
DIF[T/C]7 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
1
OE_6
OE_5
OE_4
OE_3
OE_2
OE_1
OE_0
DIF[T/C]6 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]5 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]4 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]3 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]2 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]1 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]0 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
Byte 2: Control Register 2
Bit
@pup
Name
Description
7
0
SRC_STP_DIF[T/C]7
Allow Control DIF[T/C]7 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
6
5
0
0
SRC_STP_DIF[T/C]6
SRC_STP_DIF[T/C]5
Allow Control DIF[T/C]6 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Allow Control DIF[T/C]5 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Rev 1.0,November 21, 2006
Page 4 of 15
SPECTRALINEAR [ SPECTRALINEAR INC ]
