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CY28341OC-2 参数 Datasheet PDF下载

CY28341OC-2图片预览
型号: CY28341OC-2
PDF下载: 下载PDF文件 查看货源
内容描述: 通用时钟芯片为VIA ™ P4M / KT / KM400 DDR系统 [Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems]
分类和应用: 晶体外围集成电路光电二极管双倍数据速率时钟
文件页数/大小: 18 页 / 228 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28341-2  
AC Parameters (continued)  
100 MHz  
133 MHz  
200 MHz  
Parameter  
TSKEW  
TCCJ  
Description  
Min.  
Max.  
Min.  
Max  
Min.  
Max. Unit  
250 ps 8,14  
ps 8,9,14  
Notes  
Any AGP to Any AGP Clock Skew  
AGP(0:2) Cycle-to-Cycle Jitter  
250  
500  
250  
500  
500  
55  
PCI  
T
PCI(_F,1:6) Duty Cycle  
45  
55  
45  
55  
45  
% 7,8,9  
DC  
T
PCI(_F,1:6) Period  
30.0  
12.0  
12.0  
0.5  
30.0  
12.0  
12.0  
0.5  
30.0  
12.0  
12.0  
0.5  
ns 7,8,9  
ns 8,21  
ns 8,10  
ns 8,13  
ps 8,14  
ps 8,9,14  
PERIOD  
T
PCI(_F,1:6) High Time  
HIGH  
T
PCI(_F,1:6) Low Time  
LOW  
T
T
T
/ T  
PCI(_F,1:6) Rise and Fall Times  
Any PCI to Any PCI Clock Skew  
PCI(_F,1:6) Cycle-to-Cycle Jitter  
2.5  
500  
500  
2.5  
500  
500  
2.5  
500  
500  
R
F
SKEW  
CCJ  
48 MHz  
T
48-MHz Duty Cycle  
45  
55  
45  
55  
45  
55  
% 7,8,9  
DC  
T
48-MHz Period  
20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns 7,8,9  
PERIOD  
T
T
/ T  
48-MHz Rise and Fall Times  
48-MHz Cycle-to-Cycle Jitter  
1.0  
4.0  
1.0  
4.0  
1.0  
4.0  
ns 8,13  
R
F
500  
500  
500  
ps 8,9,14  
CCJ  
24 MHz  
T
24-MHz Duty Cycle  
45  
41.660  
1.0  
55  
45  
55  
45  
55  
% 7,8,9  
DC  
T
24-MHz Period  
41.667 41.660 41.667 41.660 41.667 ns 7,8,9  
PERIOD  
T
T
/ T  
24-MHz Rise and Fall Times  
24-MHz Cycle-to-Cycle Jitter  
4.0  
1.0  
4.0  
1.0  
4.0  
ns 8,13  
R
F
500  
500  
500  
ps 8,9,14  
CCJ  
REF  
T
REF Duty Cycle  
45  
69.8413  
1.0  
55  
71.0  
4.0  
45  
55  
45  
55  
% 7,8,9  
DC  
T
REF Period  
69.8413 71.0 69.8413 71.0  
ns 7,8,9  
ns 8,13  
ps 8,9,14  
PERIOD  
T
T
/ T  
REF Rise and Fall Times  
REF Cycle-to-Cycle Jitter  
1.0  
4.0  
1.0  
4.0  
R
F
1000  
1000  
1000  
CCJ  
DDR  
V
Crossing Point Voltage of DDRT/C  
Differential Voltage Swing  
0.5*V  
DDD  
–0.2  
0.5*V  
DDD  
+0.2  
0.5*V  
DD  
–0.2  
0.5*V  
DD  
+0.2  
0.5*V  
DD  
–0.2  
0.5*V  
DD  
+0.2  
V
V
15  
23  
11  
X
D
D
D
D
V
0.7  
VDDD +  
0.6  
0.7  
VDDD +  
0.6  
0.7  
VDDD +  
0.6  
D
T
DDRT/C(0:5) Duty Cycle  
45  
9.85  
1
55  
10.2  
3
45  
55  
15.3  
3
45  
55  
10.2  
3
%
DC  
T
DDRT/C(0:5) Period  
14.85  
1
9.85  
1
ns 11  
PERIOD  
T
T
T
T
T
T
T
/ T  
DDRT/C(0:5) Rise/Fall Slew Rate  
DDRT/C to any DDRT/C Clock Skew  
DDRT/C(0:5) Cycle-to-Cycle Jitter  
DDRT/C(0:5) Half-period Jitter  
BUF_IN to Any DDRT/C Delay  
FBOUT to Any DDRT/C Skew  
All-Clock Stabilization from Power-up  
V/ns 13  
R
F
100  
75  
100  
75  
100  
75  
ps 8,14,11  
ps 8,14,11  
ps 8,14,11  
ns 8,9  
SKEW  
CCJ  
100  
4
100  
4
100  
4
HPJ  
1
1
1
DELAY  
SKEW  
STABLE  
100  
3
100  
3
100  
3
ps 8,9  
ms 22  
Ordering Information  
Part Number  
Package Type  
56-pin Shrunk Small Outline package (SSOP)  
Product Flow  
CY28341OC–2  
CY28341OC–2T  
CY28341ZC–2  
CY28341ZC–2T  
Lead-free  
Commercial, 0q to 70qC  
Commercial, 0q to 70qC  
Commercial, 0q to 70qC  
Commercial, 0q to 70qC  
56-pin Shrunk Small Outline package (SSOP)–Tape and Reel  
56-pin Thin Shrunk Small Outline package (TSSOP)  
56-pin Thin Shrunk Small Outline package (TSSOP)–Tape and Reel  
CY28341OXC–2  
CY28341OXC–2T  
56-pin Shrunk Small Outline package (SSOP)  
Commercial, 0q to 70qC  
Commercial, 0q to 70qC  
56-pin Shrunk Small Outline package (SSOP)–Tape and Reel  
Rev 1.0,November 21, 2006  
Page 17 of 18  
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