CY28341-2
Maximum Ratings[5]
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field. However,
precautions should be take to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For
proper operation, VIN and VOUT should be constrained to the
range:
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V
Storage Temperature: ................................ –65qC to + 150qC
Operating Temperature:.................................... 0qC to +70qC
Maximum ESD.............................................................2000V
Maximum Power Supply:................................................5.5V
VSS < (VIN or VOUT) < VDD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters (VDD = VDDPCI = VDDAGP = VDDR = VDD48M = VDDC = 3.3V 5%, VDDI = VDD = 2.5 5%, TA = 0°C TO +70°C)
Parameter
VIL1
Description
Input Low Voltage
Conditions
Min.
Typ.
Max. Unit
Applicable to PD#, F S(0:4)
0.8
Vdc
Vdc
Vdc
Vdc
V
VIH1
VIL2
Input High Voltage
Input Low Voltage
Input High Voltage
2.0
Applicable to SDATA and SCLK
1.0
VIH2
VOL
2.2
0.4
24
Output Low Voltage for SRESET# IOL
IOL
Pull-down current for SRESET#
Three-state leakage Current
Dynamic Supply Current
VOL = 0.4V
35
mA
PA
mA
mA
PA
PA
PA
pF
IOZ
10
190
195
600
–25
10
5
IDD3.3V
IDD2.5V
IPD
CPU frequency set at 133.3 MHz, Note 6
CPU frequency set at 133.3 MHz, Note 6
PD# = 0
150
175
95
Dynamic Supply Current
Power-down Supply current
Internal Pull-up Device Current
IPUP
IPDWN
CIN
Input @ VSS
Internal Pull-down Device Current Input @ VDD
Input Pin Capacitance
COUT
LPIN
CXTAL
Output Pin Capacitance
6
pF
Pin Inductance
7
pF
Crystal Pin Capacitance
Measured from the Xin or Xout to VSS
27
36
45
pF
AC Parameters
100 MHz
133 MHz
200 MHz
Parameter
XTAL
Description
Min.
Max.
Min.
Max
Min.
Max. Unit
Notes
TDC
Xin Duty Cycle
Xin Period
45
69.84
0.7VDD
0
55
71.00
VDD
.3VDD
10.0
500
45
55
45
55
% 7,14
ns 7,14
TPERIOD
VHIGH
VLOW
TR/TF
TCCJ
69.84
71.0
69.84
71.0
Xin High Voltage
0.7VDD VDD 0.7VDD VDD
V
V
12
15
Xin Low Voltage
0
.3VDD
10
0
.3VDD
10
Xin Rise and Fall Times
Xin Cycle to Cycle Jitter
Crystal Start-up Time
ns 13
500
30
500
30
ps 8,11
ms 10,12
TXS
30
P4 Mode CPU at 0.7V
TDC
CPUT/C Duty Cycle
CPUT/C Period
45
55
45
55
45
55
% 7,8,9,15,16
ns 7,8,9,15,16
TPERIOD
9.85
10.2
7.35
7.65
4.85
5.1
Notes:
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6. All outputs loaded as per maximum capacitive load table.
7. This parameter is measured as an average over a 1-us duration, with a crystal center frequency of 14.31818 MHz.
8. All outputs loaded as per loading specified in theTable 11.
9. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V, and 50% point for differential signals.
10. Probes are placed on the pins, and measurements are acquired at 0.4V.
11. When Xin is driven from and external clock source (3.3V parameters apply).
12. When crystal meets minimum 40-ohm device series resistance specification.
.
DD
13. Measured between 0.2V and.7V
DD
14. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
15. Measured at VX, or where subtraction of CLK-CLK# crosses 0V.
16. See Figure 10 for 0.7V loading specification.
Rev 1.0,November 21, 2006
Page 15 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
