CY28341-2
S 1
S 2
W a it fo r
1 .1 4 6 m s
S a m p le
In p u ts
F S (3 :0 )
E n a b le
O u tp u te s
D e la y 0 .2 5 m S
V D D A = 2 .0 V
S 0
S 3
N o rm a l
O p e ra tio n
P o w e r O ff
V D D 3 .3 = O ff
Figure 7. Clock Generator Power-up/Run State Diagram (with P4 processor SELP4_K7#=1)
Connection Circuit DDRT/C Signals
For open-drain CPU output signals (with K7 processor SELP4_K7#=0)
VDDCPU(1.5V)
VDDCPU(1.5V)
60.4 Ohm
3.3V
Measurement Point
ꢁꢂꢃꢀOhm
ꢂꢄꢀOhmꢀꢀ5"
500 Ohm
47 Ohm
ꢂꢄꢀOhmꢀꢀꢁ"
500 Ohm
CPUOD_T
680 pF
20 pF
3.3V
301 Ohm
ꢁꢂꢃꢀOhm
ꢂꢄꢀOhmꢀꢀ5"
VDDCPU(1.5V)
ꢂꢄꢀOhmꢀꢀ1"
47 Ohm
500 Ohm
CPUOD_C
Measurement Point
680 pF
60.4 Ohm
20 pF
500 Ohm
VDDCPU(1.5V)
Figure 8. K7 Load Termination
6”
6”
Figure 9. CS Load Termination
Table 10.Signal Loading Table
Clock Name
Max Load (in pF)
For Differential CPU Output Signals (with P4 Processor
SELP4_K7= 1)
REF (0:1), 48MHz (USB), 24_48MHz
AGP(0:2), SDRAM (0:11)
PCI_F(0:5)
20
30
30
The following diagram shows lumped test load configurations
for the differential Host Clock outputs.
DDRT/C (0:5), FBOUT
CPUT/C
See Figure 10
See Figure 8
See Figure 9
CPUOD_T/C
CPUCS_T/C
Rev 1.0,November 21, 2006
Page 13 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
