CY28341-2
AC Parameters (continued)
100 MHz
133 MHz
200 MHz
Min. Max. Unit
Parameter
TR/TF
Description
Min.
Max.
700
Min.
Max
700
Notes
CPUT/C Rise and Fall Times
Rise/Fall Matching
175
175
175
700
20%
125
ps 24
24,26
20%
125
20%
125
' TR/TF
TSKEW
TCCJ
Rise/Fall Time Variation
ps 8,24,16
ps 8,18,15,16
ps 8,18,15,16
mV 16
CPUCS_T/C to CPUT/C Clock Skew
CPUT/C Cycle to Cycle Jitter
0
200
0
150
0
200
–150
+150
430
–150
280
+150
430
–200
280
+200
430
VCROSS
Crossing Point Voltage at 0.7V Swing 280
P4 Mode CPU at 1.0V
TDC
CPUT/C Duty Cycle
45
55
45
55
45
55
5.1
467
% 8,9,15
nS 8,9,15
ps 7,14,27
TPERIOD
CPUT/C Period
9.85
175
10.2
467
7.35
175
7.65
467
4.85
175
Differential
TR/TF
CPUT/C Rise and Fall times
TSKEW
TCCJ
CPUCS_T/C to CPUT/C Clock Skew
CPUT/C Cycle to Cycle Jitter
0
200
+150
760
0
150
+150
760
0
200
+200
760
0 8,14,11
–150
510
–150
510
–200
510
ps 8,14,11
mV 27
VCROSS
Crossing Point Voltage at 1V Swing
SE-DeltaSlew Absolute Single-ended Rise/Fall
Waveform Symmetry
325
325
325
ps 26
K7 Mode
TDC
CPUOD_T/C Duty Cycle
CPUOD_T/C Period
45
9.98
2.8
55
45
7.5
55
45
5
55
% 8,9
ns 8,9
ns 8,9
ns 8,13
TPERIOD
TLOW
TF
10.5
8.0
5.5
CPUOD_T/C Low Time
1.67
0.4
2.8
0.4
0
CPUOD_T/C Fall Time
0.4
1.6
200
1.6
150
1.6
200
TSKEW
TCCJ
VD
CPUCS_T/C to CPUT/C Clock Skew
CPUOD_T/C Cycle-to-Cycle Jitter
Differential Voltage AC
0
0
0
8,14,11
ps 8,9
23
1100 mV 23
–150
0.4
+150
–150
+150
–200
+200
Vp+0.6V
1100
0.4 Vp+0.6V 0.4 Vp+.06V V
VX
Differential Crossover Voltage
500
500
1100
500
CHIPSET CLOCK
TDC
CPUCS_T/C Duty Cycle
45
10.0
0.4
55
10.5
45
15
55
15.5
1.6
45
10.0
0.4
.4
55
10.5
% 7,8,9
TPERIOD
TR / TF
VD
CPUCS_T/C Period
ns 7,8,9
CPUCS_T/C Rise and Fall Times
Differential Voltage AC
1.6
0.4
1.6
ns 7,8,13
0.4
Vp+.06V
0.4 Vp+.06V
Vp+.06V
V
V
24
11
VX
Differential Crossover Voltage
0.5*VDDI 0.5*VDDI 0.5*VD 0.5*VDDI 0.5*VD 0.5*VDDI
+0.2
–0.2
+0.2
DI–0.2
DI–0.2
+0.2
AGP
TDC
AGP(0:2) Duty Cycle
AGP(0:2) Period
45
15
55
16
45
15
55
16
45
15
55
16
% 7,8,9
ns 7,8,9
ns 8,21
ns 8,10
ns 8,13
TPERIOD
THIGH
TLOW
AGP(0:2) High Time
AGP(0:2) Low Time
AGP(0:2) Rise and Fall Times
5.25
5.05
0.4
5.25
5.05
0.4
5.25
5.05
0.4
TR / TF
1.6
1.6
1.6
Notes:
17. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals, and between
20% and 80% for differential signals.
18. This measurement is applicable with Spread ON or spread OFF.
19. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals).
20. Time specified is measured from when all VDDs reach their respective supply rail (3.3V and 2.5V) till frequency output is stable and operating within specs.
21. The typical value of VX is expected to be 0.5*V
(or 0.5*V
for CPUCS signals) and will track the variations in the DC level of the same.
DDC
DDD
22. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its complementary
DDRC (and CPUCS_C) one.
23. Measured at VX between the rising edge and the following falling edge of the signal.
24. Measured from V = 0.175V to V = 0.525V.
25. Measurement taken from differential waveform, from –0.35V to +0.35V.
OL
OH
26. Measurements taken from common mode waveforms, measure rise/fall time from 0.41V to 0.86V. Rise/fall time matching is defined as “the instantaneous
difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk# fall (rise) time”. This parameter is
designed for waveform symmetry.
27. Measured in absolute voltage, i.e., single-ended measurement.
Rev 1.0,November 21, 2006
Page 16 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
