Da ta
Shee t
(Prelimi nar y)
1.6
1.6.1
Addressing
S34ML01G1
Table 1.3
Address Cycle Map — 1 Gb Device
Bus Cycle
I/O [15:8]
I/O0
I/O1
I/O2
x8
1st
2nd
3rd
4th
—
—
—
—
A0
A8
A12
A20
A1
A9
A13
A21
A2
A10
A14
A22
x16
1st
2nd
3rd
4th
Notes:
1. L must be set to low.
2. Block address concatenated with page address = actual page address.
3. I/O[15:8] are not used during the addressing sequence and should be driven Low.
Low
Low
Low
Low
A0
A8
A11
A19
A1
A9
A12
A20
A2
A10
A13
A21
A3
L
A14
A22
A4
L
A15
A23
A5
L
A16
A24
A6
L
A17
A25
A7
L
A18
A26
A3
A11
A15
A23
A4
L
A16
A24
A5
L
A17
A25
A6
L
A18
A26
A7
L
A19
A27
I/O3
I/O4
I/O5
I/O6
I/O7
For the address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18 - A27: block address
September 6, 2012 S34ML01G1_04G1_10
Spansion
®
SLC NAND Flash Memory for Embedded
15
SPANSION [ SPANSION ]
