D a t a S h e e t ( P r e l i m i n a r y )
1.4
Block Diagram
Figure 1.5 Functional Block Diagram
Address
Register/
Counter
Program Erase
Controller
HV Generation
X
1024 Mbit + 32 Mbit (1 Gb Device)
2048 Mbit + 64 Mbit (2 Gb Device)
4096 Mbit + 128 Mbit (4 Gb Device)
D
E
C
O
D
E
R
ALE
CLE
NAND Flash
WE#
CE#
WP#
Memory Array
Command
Interface
Logic
RE#
PAGE Buffer
Y Decoder
Command
Register
I/O Buffer
Data
Register
I/O0~I/O7 (x8)
I/O0~I/O15 (x16)
September 6, 2012 S34ML01G1_04G1_10
Spansion® SLC NAND Flash Memory for Embedded
13