D a t a S h e e t ( P r e l i m i n a r y )
Figure 1.4 63-VFBGA Contact, x16 Device (Balls Down, Top View)
A2
A9
A1
A10
NC
NC
NC
NC
B1
B9
B10
NC
NC
NC
C3
C4
C5
C6
C7
C8
WP#
ALE
VSS
CE#
WE#
RB#
D3
D4
D5
D6
D7
D8
VCC
RE#
CLE
NC
NC
NC
E3
E4
E5
E6
E7
E8
NC
NC
NC
NC
NC
NC
F3
F4
F5
F6
F7
F8
NC
NC
NC
NC
VSS
NC
G3
NC
G4
G5
NC
G6
G7
G8
NC
VCC
I/O13
I/O15
H3
H4
H5
H6
H7
H8
I/O8
I/O0
I/O10
I/O12
I/O14
V
cc
J3
J4
J5
J6
J7
J8
I/O9
I/O1
I/O11
V
I/O5
I/O7
K8
CC
K3
K4
K5
K6
K7
V
I/O2
I/O3
I/O4
I/O6
V
SS
SS
L1
L2
L9
L10
NC
NC
NC
NC
M1
NC
M2
NC
M9
NC
M10
NC
1.3
Pin Description
Table 1.2 Pin Description
Pin Name
Description
I/O0 - I/O7 (x8)
I/O8 - I/O15 (x16)
Inputs/Outputs. The I/O pins are used for command input, address input, data input, and data output. The
I/O pins float to High-Z when the device is deselected or the outputs are disabled.
Command Latch Enable. This input activates the latching of the I/O inputs inside the Command Register on the rising
edge of Write Enable (WE#).
CLE
ALE
Address Latch Enable. This input activates the latching of the I/O inputs inside the Address Register on the rising
edge of Write Enable (WE#).
CE#
Chip Enable. This input controls the selection of the device. When the device is not busy CE# low selects the memory.
Write Enable. This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of WE#.
Read Enable. The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
WE#
RE#
valid t
after the falling edge of RE# which also increments the internal column address counter by one.
REA
Write Protect. The WP# pin, when low, provides hardware protection against undesired data modification
(program / erase).
WP#
R/B#
VCC
Ready Busy. The Ready/Busy output is an Open Drain pin that signals the state of the memory.
Supply Voltage. The V supplies the power for all the operations (Read, Program, Erase). An internal lock circuit
CC
prevents the insertion of Commands when V is less than V
.
CC
LKO
VSS
NC
Ground.
Not Connected.
Notes:
1. A 0.1 µF capacitor should be connected between the V Supply Voltage pin and the V Ground pin to decouple the current surges from
CC
SS
the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.
2. An internal voltage detector disables all functions whenever V is below 1.8V (3V device) to protect the device from any involuntary
CC
program/erase during power transitions.
12
Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
SPANSION [ SPANSION ]
