Data
Sheet
(Pre limin ar y)
2. Bus Operation
There are six standard bus operations that control the device: Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby. (See
Typically glitches less than 5 ns on Chip Enable, Write Enable, and Read Enable are ignored by the memory
and do not affect bus operations.
2.1
Command Input
The Command Input bus operation is used to give a command to the memory device. Commands are
accepted with Chip Enable low, Command Latch Enable high, Address Latch Enable low, and Read Enable
high and latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation
(program/erase) the Write Protect pin must be high. See
and
for
details of the timing requirements. Command codes are always applied on I/O7:0 regardless of the bus
configuration (x8 or x16).
2.2
Address Input
The Address Input bus operation allows the insertion of the memory address. For the S34ML02G1 and
S34ML04G1 devices, five write cycles are needed to input the addresses. For the S34ML01G1, four write
cycles are needed to input the addresses. If necessary, a 5th dummy address cycle can be issued to
S34ML01G1, which will be ignored by the NAND device without causing problems. Addresses are accepted
with Chip Enable low, Address Latch Enable high, Command Latch Enable low, and Read Enable high and
latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation (program/
erase) the Write Protect pin must be high. See
and
for details of
the timing requirements. Addresses are always applied on I/O7:0 regardless of the bus configuration (x8 or
x16). Refer to
through
for more detailed information.
2.3
Data Input
The Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is
serial and timed by the Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch
Enable low, Command Latch Enable low, Read Enable high, and Write Protect high and latched on the rising
edge of Write Enable. See
and
for details of the timing
requirements.
2.4
Data Output
The Data Output bus operation allows data to be read from the memory array and to check the Status
Register content, the EDC register content, and the ID data. Data can be serially shifted out by toggling the
Read Enable pin with Chip Enable low, Write Enable high, Address Latch Enable low, and Command Latch
Enable low. See
to
and
for details of the timings
requirements.
2.5
Write Protect
The Hardware Write Protection is activated when the Write Protect pin is low. In this condition, modify
operations do not start and the content of the memory is not altered. The Write Protect pin is not latched by
Write Enable to ensure the protection even during power up.
2.6
Standby
In Standby, the device is deselected, outputs are disabled, and power consumption is reduced.
18
Spansion
®
SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
SPANSION [ SPANSION ]
