Data
Sheet
(Pre limin ar y)
11.7.2
Parameter
JEDEC
Hardware Reset (RESET#)
Table 11.4
Hardware Reset (RESET#)
Std.
t
Ready
t
Ready
t
RP
t
RH
t
RPD
t
RB
Description
RESET# Pin Low (During Embedded Algorithms) to
Read Mode or Write mode
RESET# Pin Low (NOT During Embedded Algorithms)
to Read Mode or Write mode
RESET# Pulse Width
Reset High Time Before Read
RESET# Low to Standby Mode
RY/BY# Recovery Time
Min
Min
Min
Min
Min
Min
Speed
35
35
35
200
10
0
Unit
µs
µs
µs
ns
µs
ns
Figure 11.7
Reset Timings
RY/BY#
CE#, OE#
t
RH
RESET#
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
t
Ready
RY/BY#
t
RB
CE#, OE#
RESET#
t
RP
58
S29GL-P MirrorBit
®
Flash Family
S29GL-P_00_A7 November 8, 2007