A d v a n c e I n f o r m a t i o n
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (top of Figure 7).
START
Read Byte
(DQ0-DQ7)
Address = VA
Read Byte
(Note 1)
(DQ0-DQ7)
Address = VA
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ 0-DQ7)
Adrdess = VA
(Notes
1, 2)
No
DQ6 = Toggle?
Yes
FAIL
PASS
Notes:
1. Read toggle bit with two immediately consecutive reads to determine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text.
Figure 7. Toggle Bit Algorithm
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SPANSION [ SPANSION ]
