A d v a n c e I n f o r m a t i o n
AC Characteristics
Hardware Reset (RESET#)
Parameter
JEDEC
Std. Description
Test Setup
Max
All Speed Options
Unit
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
t
t
11
µs
READY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max
Min
Min
500
500
50
ns
ns
ns
READY
t
RESET# Pulse Width
RP
RESET# High Time Before Read (See
Note)
t
RH
t
RESET# Low to Standby Mode
RY/BY# Recovery Time
Min
Min
20
0
µs
ns
RPD
t
RB
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timing to Bank NOT Executing Embedded Algorithm
Reset Timing to Bank Executing Embedded Algorithm
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 19. RESET# Timings
78
S29CD032G
30606B0 March 22, 2004
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