A d v a n c e I n f o r m a t i o n
AC Characteristics
Erase Command Sequence (last two cycles)
Read Status Data
tAS
SA
tWC
VA
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status).
Figure 22. Chip/Sector Erase Operation Timings
tWC
Valid PA
tWC
tRC
tWC
Valid PA
tAH
Valid RA
Valid PA
Addresses
tCPH
tACC
tCE
CE#
OE#
tCP
tOE
tOEH
tGHWL
tWP
tWPH
WE#
Data
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Valid
In
Valid
In
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE# Controlled Write Cycles
Figure 23. Back-to-back Cycle Timings
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S29CD032G
30606B0 March 22, 2004
SPANSION [ SPANSION ]
