A d v a n c e I n f o r m a t i o n
AC Characteristics
CLK
ADV#
CE#
tCS
tCH
Stable Address
Addresses
Data
tWC
Valid Data
tAH
tAS
tDH
tDS
WE#
OE#
tOEH
tWPH
IND/WAIT#
Figure 17. Asynchronous Command Write Timing
Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the
READ/RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses
are burst mode when the burst mode option is enabled in the Configuration Register.
CE#
tCES
CLK
tADVCS
tADVP
ADV#
tACS
tACH
tACH
Valid Address
tWC
t
tACS
AS
Addresses
Data
Valid Address
tEHQZ
tADVCH
Data In
tWADVH
Data Out
tDF
tWCKS
tDH
tOE
OE#
WE#
tDS
tWP
10 ns
IND/WAIT#
Figure 18. Synchronous Command Write/Read Timing
Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/
RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are burst
mode when the burst mode option is enabled in the Configuration Register.
March 22, 2004 30606B0
S29CD032G
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SPANSION [ SPANSION ]
